Introduction of Rectifier

OBJECTIVE:-

To design and set up the following rectifiers with and without filters and to determine ripple factor and rectifier efficiency.

THEORY:-

 CENTRE TAP FULL WAVE RECTIFIER

During positive half cycle of the input voltage, the diode D1 is forward biased and conducts and diode D2 is reverse biased and will not conduct. The current will flow through the direction A-B-C-D-E. During negative half cycle diode D2 is forward biased and conducts. Diode D1 is reverse biased and will not conduct. The current will flow through the direction F-B-C-D-E. There fore during both half cycles i.e., positive and negative half cycles the out put current will be in only one direction.

Fig:- Centre tap full wave rectifier

FULL WAVE BRIDGE RECTIFIER

During positive half cycle of the input voltage, the diode D1 and D3 is forward biased and both diodes will conduct and diode D2 and D4 is reverse biased and will not conduct. The current will flow through the direction A-B-C-D-E-F-G.

During negative half cycle, the diode D2 and D4 is forward biased and both diodes will conduct and diode D1 and D3 is reverse biased and will not conduct. he current will flow through the direction G-F-C-D-E-B-A. There fore during both half cycles i.e., positive and negative half cycles the out put current will be in only one direction i.e., from point C to D.

Fig:-full wave bridge rectifier

DESIGN:- (Common for both rectifiers)

For the transformer, primary voltage VP=230 V  Secondary voltage VS=12V  Voltage across diode VD = 0.6 V (Silicon transistor)  For a diode current of 10mA, i.e., ID = 10mA

\( R_L=[V_S-V_D]/I_D \)​= [12 – 0.6] / 10mA = 1.14 KΩ ; choose RL = 1 KΩ  With capacitor filter, ripple factor

Allowing 3% ripple, i.e., r=0.03, f = 50 Hz, RL = 1 KΩ we get C = 96.225µF, let C=100 µF Vm = 12×Ö2 = 16.97 V (Maximum value of the sinusoidal voltage applied to the rectifier) Vdc = 2Vm/π = 10.8V (For the rectifier without filter, Theoretical)

Idc = Vdc/RL (DC Current through the load)

Idc = 10.8V/47W = 229.78 mA (Full Load current, min value of RL shown in the Table, with RS= Rf =0),

Pdc= Vdc2/RL (Load Power)

Pac= VS×IS (Power supplied by the transformer) Ripple factor γ = Vac/Vdc (=1.21 Theoretical) %Efficiency = Pdc/Pac ((40.6%, Theoretical)

%Regulation = E = (VNL-VFL)/VFL

CIRCUIT DIAGRAM OF RECTIFIER:-

Fig:-Center tap full wave rectifier with filter (remove C for rectifier without filter)

Fig:-Full wave bridge rectifier with filter (remove C for rectifier without filter

APPERATUS TABLE:-

Sl.no Apperatus used name Quantity Specification Maker name
1 Center tapped transformer 1 12V-0V-12V
2 diodes 2 IN4007
3 Resistors 2 10Ω
4 Multimeter 1
5 CRO 1
6 Bread board 1

 

PROCEDURE:-

  1. Place the components on bread board and connect them as per circuit diagram.
  2. Connect minimum output resistance and DRB in series
  3. Switch on the input ac and note down readings. Tabulate the readings for different values of output resistor and find out ripple factor, load regulation, and efficiency.
  4. Using CRO measure the output wave form and check whether it matches with required wave form.
  5. Repeat this experiment for by connecting the suitable capacitor across the load to reduce the ripple to less than 3%

OBSERVATION:-

For both rectifiers use similar tabular column separately

1.Tabular column for rectifier without filter

RL VM(Use CRO) Vdc the theoretical Vdc=2vm Vdc practical use multi-meter in dc mode Vdc practical use multi-meter in ac mode Vrms=Vm/√2 ϒ=Vac/Vdc η=V2dc/V2rms
1kΩ
2kΩ
3kΩ
4kΩ
5kΩ

 

2.Tabular column for rectifier with filter

RL VM(Use CRO) Vr.pp(Use CRO) Vrms the theoretical Vr.rms=Vr.pp/2√3 Vdc the theoretical Vdc=vm-(Vr.pp/2) Vdc Practical use multi-meter in dc mode γ=Vr.rms/Vdc η=V2dc/V2rms
1kΩ
2kΩ
3kΩ
4kΩ
5kΩ

 

GRAPH:-

RESULT:-

 

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