Study of Phase locked loop

Objective:

To find out the lock range and capture range of PLL.

Theory:

Block diagram of PLL is shown in fig.1. VCO is a free running multivibrator and operates at a set frequency f0 called free running frequency. This frequency is determined by an external timing capacitor and an external resistor. It can also be shifted to either side by applying a dc control voltage vc to an appropriate terminal of the IC. The frequency deviation is directly proportional to the dc control voltage and hence it is called a “Voltage Controlled Oscillator” or VCO. If an input signal vs of frequency fs is applied to the PLL, the phase detector compares the phase and frequency of the incoming signal of that to the output vo of the VCO.  If the two signals differ in frequency and/or phase, an error voltage ve is generated. The phase detector is basically a multiplier and produces the sum (fs+f0) and the difference (fs-f0) components at its output. The high frequency component (fs+f0) is removed by the low pass filter and the difference frequency component is amplified and then applied as control voltage vc to VCO. The signal vc shifts the VCO frequency in a direction to reduce the frequency difference between fs and f0. Once this action starts, we say that the signal is in the capture range. The VCO continues to change frequency till its output frequency is an exactly the same as the input signal frequency. The circuit is then said to be locked. Once locked, the output frequency f0 of VCO is identical to fs except for a finite phase difference φ. This phase difference φ generates a corrective control voltage vc to shift the VCO frequency from f0 to fs and thereby maintain the lock. Once locked, PLL tracks the frequency changes of the input signal.

Thus, a PLL goes through three stages (i) free running, (ii) capture and (iii) locked or tracking.

Lock in range: Once the PLL is locked, it can track the frequency changes in the incoming signals. The range of frequencies over which the PLL can maintain lock with the incoming signal is called the lock in range. It is expressed as a percentage of f0, the VCO frequency.

Capture range: The range of frequencies over which the PLL can acquire lock with an input signal is called the capture range.

Pull-in Range: Δ fP = |fi−fO| is the maximum initial frequency difference between the input and VCO center frequencies both in positive and negative directions, for which the PLL eventually achieves the phase-locked condition. The pull-in range is related to the dynamics of the PLL.

Hold-in Range: Suppose the phase-locked condition has been achieved in the PLL. Now vary the input frequency fi slowly and the VCO frequency will follow it. The hold-in range Δ fH = |fi−fO|   is determined by the lower and upper values of fi, for which the phase-locked condition is lost. The hold-in range represents the maximum static tracking range.

The equation of VCO frequency, lock range and capture range are given below.

fO = 0.3/R1 C1

f lock = ± (8fo/VCC)

f capture = ±(1/2π) √ (2π f lock / 3600C2)

Apparatus required: Procedure:

• The pin diagram and the circuit diagram of is shown in  fig 2 and fig. 3 respectively. Build the circuit on bread board according to the diagram. The ideal value of C1 and C2 would be 220pF and 300pF respectively. But we can use 0.001µF and 0.1µF for C1 and C2 also. R1= 4.7KΩ. Fig.2 Pin diagram of PLL (LM 565) • First see the VCO output in CRO and measure its frequency.
• Then take a square wave from the function generator (use the output knob of function generator) and connect it at pin 2 of the IC as input signal. If you use 0.001µF and 0.1 µF for C1(timing capacitor) and C2(low pass filter capacitor) and 4.7KΩ as R1(timing resistor), set the input signal frequency much lower than the VCO output frequency.
• Now increase the input signal frequency by 0.1 KHz using the frequency changing knob in the function generator and see the signal in CRO.
• Keep changing the input signal frequency. In CRO simultaneously see the two signals- VCO output signal and the input signal from function generator.
• When changing the input signal frequency, a moment will come when both signals will have same frequency i.e. the two signals will be locked. Note that frequency as capture lower frequency.
• Now increase the frequency of the input signal. Then we will see two signals are such that there is no phase difference between them up to certain time.
• After getting the capture upper frequency, start decreasing the input signal frequency. Then again, we will see two signals are such that there is no phase difference between them up to certain time.
• At some point the two signals will be unlocked. Note this frequency as lock lower frequency.
• After some time, there will be a moment when the lock condition breaks. This means the two signals now have different frequency. Note this frequency as lock upper frequency.
• Now increase the frequency a little and then start decreasing until the two signals are locked again. Note this frequency as capture upper frequency.
•  Repeat step 5-11 four times. Fill up the observation table given below. Then find out the average of each frequency.

Experimental results: Discussion:

Be careful when changing the frequency. Precise measurements should be taken. Otherwise error will occur.